1. Field of the Invention
The present invention generally relates to pulse width modulated (PWM) inverters and, more particularly, to an enhanced real-time control of a PWM inverter which monitors output harmonics and reduces output harmonics by a vernier change in position of a single switching angle.
2. Description of the Prior Art
PWM inverters are employed to convert direct current (d.c.) to alternating current (a.c.). In many applications, it is important to carefully regulate the quality of the a.c. generated by the inverter. Accordingly, it is customary to define a point of regulation (POR) downstream of the inverter at which the voltage and current of the a.c. signal generated by the inverter is sampled. The sampled voltage and current would be used to select appropriate PWM switching patterns to minimize distortion at the POR. Based on the voltage and current sensed at the POR, and in some systems also link ripple, an inverter controller selects one PWM pattern from a number cf stored patterns (or creates a pattern in real time) to provide the least harmonic distortion at the POR. As real and reactive power factors of electrical loads coupled to the inverter change, the PWM pattern used to control to the inverter switches change. A PWM pattern comprises a set of switching transients which, when applied to a d.c. signal via an inverter, produces alternating pulses which, when filtered, approximates a sinusoidal a.c. signal. The pulses in a PWM pattern are of varying width. Normally, the inverter can adequately reproduce the PWM pattern and thereby create an accurate approximation of a sinusoidal a.c. signal from the d.c. voltage. However, under some load conditions (particularly when loads are unbalanced or have particular real or reactive power components), the inverter controller selects a PWM pattern which has switching transients defining pulses which cannot be faithfully reproduced by the inverter due to physical limitations of transistor switches therein. In other words, the transistor switches within the inverter have physical limitations which manifest themselves, among other ways, in a minimum allowable switching time. Thus, should the inverter switch be called upon to switch faster than it is able, it will be unable to do so and, therefore, will be unable to faithfully reproduce a part of the PWM pattern required to maintain the least distortion at the POR. Accordingly, under some conditions, the POR cannot be regulated due to physical limitations of the transistor switches in the inverter. In addition, the wide range of link ripple and load variation require more patterns than can economically be stored if a reasonable degree of regulation is required. Thus, it is not practical to select a new pattern for small changes in load conditions.
Prior inventions have addressed schemes for controlling current and voltage at the POR. Representative of such inventions is U.S. Pat. No. 4,527,226 to Glennon, which discloses an inverter control system for a PWM inverter circuit. This circuit comprises an angle set look up table and selection logic for addressing the look up table. The angle set defining the inverter output waveform is selected in response to various operating conditions of the inverter.
An earlier patent to Glennon, U.S. Pat. No. 4,382,275, is directed to a PWM inverter having an output signal with reduced harmonic content, wherein a filtered fundamental PWM signal is summed with a controlled signal.
U.S. Pat. No. 4,595,976 to Parro, II discloses an inverter control which is an enhancement of the Glennon inverter control. More specifically, the table look up is implemented as a plurality of memories, one for each phase, each of which is subdivided into a plurality of memory blocks which store a number of bytes. Memory address decoding logic addresses a particular memory block in each memory in accordance with a control signal representing the desired waveform to be generated at each phase output. Thus, the Parro, II inverter control accomplishes individual phase regulation of the inverter output.
U.S. Pat. No. 4,635,177 to Shekhawat et al., discloses a further refinement of the basic Glennon inverter control system. More specifically, the Shekhawat et al., control permits on-line generation of PWM patterns for a neutral point clamped PWM inverter. A microprocessor and memory are coupled to the generating circuitry for calculating switching points for the inverter switches during operation of the inverter. Timer modules are coupled to the microprocessor for developing switch points so that the switches are operated to reduce the distortion of the inverter output signal.
U.S. Pat. No. 4,480,299 to Muto et al., also discloses a microprocessor controller inverter control. However, the Muto et al., PWM inverter is controlled by the use of the fundamental wave voltage of the inverter output as a feedback quantity. Muto et al. fail to show any apparatus for directly dealing with the physical limitations within the inverter itself.
Other patents related to the art of inverters include U.S. Pat. Nos. 3,648,150 to Kerick et al., and 4,626,979 to JaQuay. The Kerick et al., patent discloses an apparatus for comparing a filtered output of a PWM inverter with a reference waveform and generating output voltage signal to control the inverter drive circuit to produce an output waveform substantially duplicating the reference waveform. The JaQuay patent is similar to the Kerick et al. patent in that it is directed to a PWM inverter, including a comparator for comparing an output voltage with the sum of a reference voltage and a maximum allowable ripple voltage.
Also representative of the prior art are U.S. Pat. Nos. 4,646,221 to Sekino et al., 4,757,434 to Kawabata et al., 4,800,478 to Takahashi, and 4,757,432 to Hancock. The patent to Sekino et al., is directed to a controlling circuit which monitors the output waveform of the inverter and controls the firing of the switch elements in the inverter to restore it to a sinusoidal waveform in the event that it is distorted by nonlinear loads. The patent to Kawabata et al., is directed to a control circuit for a current control minor loop which monitors the instantaneous value of the output current of the power conversion apparatus and adjusts it to the current reference value. The patent to Takahashi is directed to a control for an inverter, wherein an evaluation function on the whole combination of the inverter and the load connected to the a.c. side of the inverter is minimized. The patent to Hancock is directed to a device for time integrating the difference between the electrical output and the reference by varying the switching frequency in the inverters so as to null the time integrated difference in a feedback control loop.